The present invention relates generally to a solid state memory device, and is specially relates, although not restricted, to a semiconductor memory device including a redundant circuit which may operate to switch a normal memory cell to a redundant memory cell within a memory cell array formed of a plurality of normal and redundant memory cells disposed in the form of a matrix.
Along with the restless demand for increase in the memory capacity of the semiconductor memory device such as a random access memory (RAM), it has become a serious problem that some defective memory cells in the memory cell array lowers the throughput of the memory device. In order to overcome this problem, addition of a redundant circuit has been proposed as a countermeasure, in which the memory column or row including the defective memory cells is replaced by the redundant memory column or row, thereby improving the throughput of the memory array. The semiconductor memory device having the redundant circuit like this is disclosed in a Japanese unexamined patent publication No. 63-292500 which is incorporated by reference.
The prior art semiconductor memory device 101 having a redundant circuit will now be described in the following, with reference to FIGS. 6 and 7 of the accompanying drawings. As shown in the figures, the semiconductor memory device 101 is provided with an address buffer circuit 103, a memory cell array 105, a decoder 107, address program circuits 111, 112, 113, and 114, a redundant enable circuit 117, inverters 121, 122, 123, 124, and 127, and a NAND gate 129. The following description will be made with regard to a particular case where the memory cell array 105 of the semiconductor memory device 101 is provided with four redundant memory rows SR1, SR2, SR3, and SR4.
The address buffer circuit 103 has the function of generating a complementary internal address signal (a0, /a0), (a1, /a1), . . . , (an, /an) based on an address signal A0, A1, . . . , An which is externally supplied to the semiconductor memory device 101. Internal address signal a0, a1, . . . , an is inputted to the decoder 107 and address program circuits 111, 112, 113, and 114, respectively. Furthermore, the semiconductor memory device 101 is made up such that the above internal address signal a0, a1, . . . , an and the complementary signal /a0, /a1, . . . , /an thereto are inputted to address program circuits 111, 112, 113, and 114, respectively.
The decoder 107 has the function of outputting a selection signal X for selecting a predetermined normal memory row RRn in the memory cell array 105 based on the above internal address signal a0, a1, . . . , an.
On one hand, output terminals of address program circuits 111, 112, 113, and 114 are connected with input terminals of inverters 121, 122, 123, and 124, and also with four input terminals of the NAND gate 129, respectively.
Furthermore, the semiconductor memory device 101 is made up such that enable signals /EN1, /EN2, /EN3, and /EN4 from the redundant enable circuit 117 are respectively inputted to address program circuits 111, 112, 113, and 114.
The inverter 121 is made up to output a selection signal RE1 for selecting the redundant memory row SR1 in the memory cell array 105 in response to the signal /RE1 from the address program circuit 111. In the same way, inverters 122, 123, and 124 are made up to output selection signals RE2, RE3, and RE4 for selecting the redundant memory rows SR2, SR3, and SR4, respectively.
The output terminal of the NAND gate 129 is connected with the input terminal of the inverter 127 and is made up to output a signal R in response to signals /RE1, /RE2, /RE3, and /RE4 inputted thereto. The inverter 127 is made up to output an enable signal /R to the decoder 107 in response to the signal R inputted thereto from the NAND gate 129.
In the next, the structure of address program circuits 111, 112, 113, and 114 will be described in the following, with reference to FIG. 7. Respective structures and functions of these address program circuits 111, 112, 113, and 114 are almost identical to each other, so that the following description will be made only in terms of the address program circuit 111 as a representative from the remainders.
The address program circuit 111 includes NOR gates G0-1, G0-2, G1-1, G1-2, . . . , Gn-1, and Gn-2, fuses F0-1, F0-2, F1-1, F1-2, . . . , Fn-1, and Fn-2, and a NAND gate 131. A pair of NOR gates G0-1 and G0-2 correspond to complementary internal address signals a0 and /a0 i.e. the address signal A0. In the same way, a pair NOR gates G1-1 and G1-2 correspond to the address signal A1, and a pair of NOR gates Gn-1 and Gn-2 corresponds to the address signal An. Also, a pair of fuses F0-1 and F0-2 correspond to the address signal A0. In the same way, a pair of fuses F1-1 and F1-2 correspond to the address signal A1, and a pair of fuses Fn-1 and Fn-2 corresponds to the address signal An.
The enable signal /EN from the redundant enable circuit 117 is inputted to one input terminal of respective NOR gates G0-1, G0-2, G1-1, G1-2, . . . , Gn-1, and Gn-2. Internal address signals a0, /a0, a1, /a1, . . . , an, and /an are inputted to the other input terminal of respective NOR gates G0-1, G0-2, G1-1, G1-2, . . . , Gn-1, and Gn-2.
Each output terminal of NOR gates G0-1, G0-2, G1-1, G1-2, . . . , Gn-1, and Gn-2 is correspondingly connected with one end of respective fuses F0-1, F0-2, F1-1, F1-2, . . . , Fn-1, and Fn-2.
The other ends of fuses F0-1 and F0-2 are commonly connected with the first input terminal of the NAND gate 131. Furthermore, the other ends of fuses F1-1 and F1-2 are commonly connected with the second input terminal of the NAND gate 131. In the same manner, the other ends of respective fuses F2-1 and F2-2 through Fn-1 and Fn-2, are commonly and correspondingly connected with the third through nth input terminals of the NAND gate 131.
This structure enables the NAND gate 131 to output the signal /RE1 to the downstream inverter 121 as shown in FIG. 6.
Operation of the prior art semiconductor memory device 101 as constructed above, will be described in the next.
Here, the preliminary probe check or the like is carried out over the memory cell array 105 of the semiconductor memory device 101. If one defective memory cell has been detected by this check for instance, the address program circuit 111 is initialized corresponding to the address signal A0, A1, . . . , An of the detected defective memory cell (referred to as `defective address`0 hereinafter). More specifically, either one of a pair of fuses F0-1 and F0-2, F1-1 and F1-2, . . . , Fn-1 and Fn-2, is selectively cut off by a suitable means such as laser rays, thereby causing the enable signal /EN1 from the redundant enable circuit 117 to enter its ON-state (L-level) and also causing the signal /RE1 from the address program circuit 111 to enter its ON-state (L-level) only when the defective address A0, A1, . . . , An is inputted to the semiconductor memory device 101.
With initialization of the address program circuit 111, if the defective address A0, A1, . . . , An is inputted to the semiconductor memory device 101, the NAND gate 129 receives the L-level signal /RE1 from the address program circuit 111, so that it comes to output a H-level signal R to the inverter 127. As a result of this, the inverter 127 outputs the L-level enable signal /R to the decoder 107, thereby the selection signal X i.e. the output from the decoder 107 for selecting the predetermined normal memory row RRn, coming to enter its OFF state.
On one hand, the inverter 121 outputs the H-level selection signal RE1 upon receipt of the L-level signal /RE1 from the address program circuit 111 and selects the redundant memory row SR1. As explained in the above, the prior art semiconductor memory device 101 is constructed such that when it receives the defective address A0, A1, . . . , An, the redundant memory row SR1 is selected instead of the normal memory row including the defective memory cell. Furthermore, if two or more defective memory cells are detected in the memory cell array 105, redundant memory rows SR2, SR3, and SR4 are selected by means of address program circuit 112, 113, and 114, thus making it possible to execute redundancy remedy of the semiconductor memory device.
As discussed in the above, the prior art semiconductor memory device 101 requires the complementary internal address signal (a0, /a0), (a1, /a1), . . . , (an, /an) corresponding to the address signal A0, A1, . . . , An supplied externally thereto. Consequently, the number of internal address signals generated by the address buffer 103 becomes two times as many as that of the address signals which are inputted externally.
In respect of the semiconductor memory device, especially one having a larger memory capacity, improvement in its throughput is recently becoming a more important issue which manufacturers and users of semiconductor devices are very much interested in. Therefore, redundancy technology increases its importance in connection with remedy of the defective memory cell in the memory cell array.
However, in case of the semiconductor memory device having a memory capacity of mega bits class, more than 30 bits have to be prepared for use in the internal address signal. This would naturally causes increase in the pattern area of the chip, which in turn leads to a problem of increase in the chip size.